Lowering the Barrier to Chiplets

By Zero ASIC

February 7, 2024

Chiplets are all the rage these days, even making MIT Technology Review's 10 Breakthrough Technologies of 2024. This is pretty incredible for such a niche technology! Unfortunately, as of today chiplets are only accessible to semiconductor mega-corps. To unlock the true power of disaggregated chiplet innovation, we need to drastically reduce the barriers to chiplet based design.

One of the barriers to chiplets is the high cost and complexity of die-to-die interfaces. Existing die-to-die electrical interfaces (eg. AIB, UCIe, BoW) are designed to be simple, yet the cost of implementation (or procurement) has remained prohibitive. For chiplets to really take off, we need chiplet interfaces that are small, cheap, and fast.

To this end, we have created a low complexity (and low cost) prototype implementation of the UCIe standard, suitable for a wide range of technology nodes. The interface was designed and simulated entirely using open source EDA tools.

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