Advancements in TSMC's CoWoS Technology to Enable Massive System-in-Packages by 2027

By Aabachy.com (April 30, 2024)

TSMC is developing an enhanced version of its chip-on-wafer-on-substrate (CoWoS) packaging technology that will support system-in-packages (SiPs) over two times larger, the company disclosed at its North American Technology Symposium. These new packages will be massive, measuring 120x120mm, and will consume kilowatts of power, according to TSMC's projections.

The latest iteration of CoWoS technology allows TSMC to fabricate silicon interposers that are approximately 3.3 times larger than a photomask (858mm2). This enables logic, eight HBM3/HBM3E memory stacks, I/O, and other chiplets to occupy up to 2831 mm2 of space. The maximum substrate size is set at 80×80 mm. Notably, both AMD's Instinct MI300X and Nvidia's B200 utilize this technology, with Nvidia's B200 processor being larger than AMD's MI300X.

The upcoming CoWoS_L technology, expected to be operational by 2026, will support interposers around 5.5 times the size of a photomask, providing 4719 mm2 for logic, up to 12 HBM memory stacks, and other chiplets. These SiPs will necessitate larger substrates, likely 100x100 mm based on TSMC's plans, thus ruling out the use of OAM modules.

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