Chiplet IP Standards Are Just The Beginning
By Ann Mutschler, Semi Engineering (March 6th, 2024)
Data and protocol interoperability standards are needed for EDA tools, and there are more hurdles ahead. Customized chiplets will be required for AI applications.
Experts at the Table: Semiconductor Engineering sat down to talk about chiplet standards, interoperability, and the need for highly customized AI chiplets, with Frank Schirrmeister, vice president solutions and business development at Arteris; Mayank Bhatnagar, product marketing director in the Silicon Solutions Group at Cadence; Paul Karazuba, vice president of marketing at Expedera; Stephen Slater, EDA product management/integrating manager at Keysight; Kevin Rinebold, account technology manager for advanced packaging solutions at Siemens EDA; and Mick Posner, vice president of product management for high-performance computing IP solutions at Synopsys. What follows are excerpts of that discussion. To view part one of this discussion, click here.
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X
- Keysight Expands Chiplet Interconnect Standards Support in Chiplet PHY Designer 2025
- Wave Photonics Acquires Phoelex Chiplet IP to Power Datacoms & AI Growth
- BOS Joins VESA and UCIe to Advance Global Standards in Display and Chiplet Technology
Latest News
- Chiplet Summit 2026 to Spotlight AI Acceleration and Advanced Packaging
- GlobalFoundries Acquires Advanced Micro Foundry, Accelerating Silicon Photonics Global Leadership and Expanding AI Infrastructure Portfolio
- PowerLattice Raises $25 Million to Break the AI Power Wall
- Alphawave Semi Showcases Advances in PCIe Over Optics and Chiplet Integration at SC25
- Avicena Advances microLED and Photo Detector Arrays to Enable the World’s Lowest-Power AI Scale-up Optical Interconnects