World’s first UCIe heterogeneous chiplet test chip
By Nick Flaherty, eeNews Europe (December 18, 2023)

Synopsys and Intel have developed the first test chip with the Universal Chiplet Interconnect Express (UCIe) protocol used to connect chiplets made on different processes.
The test chip demonstrated UCIe traffic between Synopsys UCIe PHY IP and Intel UCIe PHY IP, simulating each test chip using the Synopsys VCS functional verification tool.
Intel’s test chip, Pike Creek, consists of an Intel UCIe IP chiplet fabricated on Intel 3 technology and was paired with a Synopsys UCIe IP test chip fabricated on the TSMC N3 process. The successful pairing mimics the mixing and matching of dies that can occur in real-world multi-die systems, demonstrating that this approach is commercially viable.
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related News
- PseudolithIC Inc. Raises $6M in Seed Funding to Revolutionize Wireless Chips with Proprietary Chiplet Heterogeneous Integration Technology
- Ayar Labs Unveils World's First UCIe Optical Chiplet for AI Scale-Up Architectures
- Analogue Insight and Tetrivis Announce Joint Development of “Eurytion RFK1”, a UCIe based 12 nm Ka/Ku-Band RF Chiplet Transceiver
- BOS Joins VESA and UCIe to Advance Global Standards in Display and Chiplet Technology
Latest News
- Avicena Launches the World’s First microLED Optical Interconnect Evaluation Kit for AI Infrastructure Innovators
- Lightmatter Achieves Record 1.6 Tbps Per Fiber to Accelerate AI Optical Interconnect
- Arm Positions Neoverse for AI and Telco Networks at MWC
- NVIDIA Compute Architecture Paves the Way for Scale-Up Optical Interconnects; CPO Penetration in AI Data Centers Expected to Rise Steadily
- CEA-Leti and NcodiN Partner to Industrialize 300 mm Silicon Photonics for Bandwidth-Hungry AI Interconnects