UCIe 3.0 Adds DSP Support

By Gary Hilson, EETimes | September 26, 2025

The ubiquity of chiplets and their diverse usages drove the formation of a consortium to develop and oversee standards, so it should come as no surprise that the latest update addresses a specific, emerging market segment.

In a briefing with EE Times, Debendra Das Sharma, UCIe Consortium chairman, stated that the updates in version 3.0 aim to address ecosystem demands and the requirements of the consortium’s 140 member companies, as well as the needs of high-performance computing (HPC) and artificial intelligence (AI) systems.

Two years ago, the consortium released UCIe 1.1 to address automotive compliance requirements, while 2.0 added support for 3D chiplets. Das Sharma said the release of 2.0 also addressed issues around testing and debugging, including concerns resulting from the reduction of bump pitches, as well as firmware upgrades. “That’s not an interconnect problem per se, but that’s a problem that needs to be solved,” he said.

UCIe 3.0 aims to double the bandwidth, Das Sharma said. “We basically double the data rate with the planar interconnect, and that’s because people can’t get enough bandwidth.” Getting more bandwidth is accomplished by shrinking bumps further. “If the bump is reduced, then my bandwidth actually quadruples,” he said. “But that requires more on the process side.”

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