Partitioning In The Chiplet Era

By Ann Mutschler, SemiEngineering (October 3, 2024)

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

The widespread adoption of chiplets in domain-specific applications is creating a partitioning challenge that is much more complex than anything chip design teams have dealt with in previous designs.

Nearly all the major systems companies, packaging houses, IDMs, and foundries have focused on chiplets as the best path forward to improve performance and reduce power. Signal paths can be shortened with proper floor-planning, and connections between chiplets and memories can be improved to reduce resistance and capacitance, which in turn can reduce the overall power. 

To read the full article, click here