Optical Chiplet Interconnect Promises to Accelerate Computing Apps
By Alix Paultre, ElectronicDesign (September 17, 2024)
Avicena’s founder and CEO breaks down the challenges of intra-chip data management and how his company’s LightBundle platform offers a solution.
To read the full article, click here
Related Chiplet
- Optical Chiplet
- Reverse Gearbox Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
Related News
- Ayar Labs to Showcase Optical Interconnect Solutions to Redefine AI Infrastructure at OFC 2024
- ISSCC 2025: Intel Propels Chiplet Interconnect Speed and Flexibility
- Avicena Announces Modular LightBundle™ Optical Interconnect Platform with > 1Tbps/mm I/O density and < 1pJ/bit
- Ayar Labs Unveils World's First UCIe Optical Chiplet for AI Scale-Up Architectures
Latest News
- Innolux's Deployment of Key FOPLP Technologies: Leading Next-Gen Advanced Packaging and Seizing AI Opportunities
- Wiwynn, Ayar Labs, and GUC Advance Co-Packaged Optics with Live Demonstration of Integrated Optical Compute System at OCP Global Summit 2026
- ForwardEdge ASIC Announces UCIe 3.0 IP Solution to Accelerate Next-Generation Chiplet-Based ASIC Innovation
- Eliyan Introduces NuLight™: World’s First 2D microVCSEL Interconnect Solution to the Copper Wall
- Evatec delivers first CLUSTERLINE® 310 for Advanced Packaging on small panel formats