Chiplet-Based FPGAs Optimize Performance for Space Applications

Partitioning compute and I/O simplifies design for greater reliability and flexibility.

By Giordana Francesca Brescia, embedded.com

Field-programmable gate array (FPGA) architectures for space must reconcile computing capacity, reliability, power consumption, and component availability for very long missions. A chiplet-based approach can separate processing and I/O, allowing for the optimization of radiation tolerance, performance, and upgradeability.

Beyond the monolithic FPGA

Space applications require increasingly higher processing capacities, especially in payloads dedicated to Earth observation, scientific data processing, and high-speed communication systems. The FPGA continues to be considered a particularly interesting platform because it allows developers to implement parallel pipelines, hardware accelerators, and reconfigurable interfaces without resorting to a dedicated application-specific IC.

The increase in complexity, however, introduces an architectural problem that is difficult to ignore. Concentrating all functions in a single die means associating performance, interfaces, and the surface exposed to radiation with the same technological process and the same level of qualification. Reliability and radiation tolerance are specific requirements for FPGAs in space, while long development cycles and component availability make full lifecycle management particularly important.

One possible evolution is to adopt a chiplet structure in which the FPGA system is decomposed into multiple specialized dies connected through an advanced package. The goal is not simply to physically divide a monolithic device but to separate functions with different requirements, making the computational logic, memory, interfaces, and service circuits independent, at least in part.

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