Rapid AI and HPC Requires Collaboration and Co-optimization

Martijn Pierik, Kiterocket
EETimes (June 13, 2024)

I recently attended the IEEE 74^th Electronic Components and Technology Conference (ECTC) in Denver, Colorado. Held May 28-31, the event had an attendance of 2,000 registrants over four days. There were 379 technical papers presented, many with a focus on hybrid bonding, substrate scaling technologies for chiplets, and other key challenges related to the critical role that advanced packaging plays in enabling the fast-growing AI and high-performance computing (HPC) markets.

To say it bluntly, advanced packaging is sexy! From Taiwan Semiconductor Manufacturing Co. (TSMC) and Intel to Google and Meta, everyone was present because these are the technologies we need to power the next industrial revolution: AI.

In her keynote address, Keren Bergman of Columbia University discussed the unprecedented growth of AI applications in data centers—growing at a rate of six orders of magnitude in the last six years—and the need for optical interconnect technologies to increase energy efficiency and bandwidth density. Her presentation, “Petascale Photonic Chip Connectivity for Energy-Efficient AI Computing,” made a strong case for bringing photonics into compute sockets using heterogenous integration—a technology she expects to become commercially available no sooner than 2027.

Hybrid bonding was another hot topic covered widely at the conference; it is expected to be the successor to microbumps in devices requiring high-bandwidth data transmission. However, there are still a number of challenges that need to be addressed.

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