AI Drives Larger, Denser Packaging, Raising New Challenges for Equipment Makers
By Susan Hong, EE Times | September 30, 2026

Artificial intelligence is pushing advanced packaging in seemingly opposite directions: Package sizes are getting larger, while interconnect pitches and defect tolerances continue to shrink.
At A*STAR’s Innovate Together 2026 in Singapore, experts from KLA, ASM, ASMPT, and the National University of Singapore (NUS) discussed how advanced packaging is evolving beyond individual equipment or process technologies. The challenge is to integrate materials, bonding, metrology and inspection, optical interconnects, and system design while maintaining yield, reliability, and cost efficiency across larger package areas and finer interconnect pitches.
Surya Bhattacharya, head of system-in-package at A*STAR’s Institute of Microelectronics (IME) and moderator of the panel, said that as continued transistor scaling becomes insufficient to meet AI computing demands, systems must integrate more dies and functions, making packaging an increasingly integral part of system design.
To read the full article, click here
Related Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
Related News
- Applied Materials Introduces New Systems to Accelerate DRAM and Advanced Packaging for AI Chips
- AI Boom Drives Demand for Ultra-Large Packaging as ASICs Expected to Shift from CoWoS to EMIB, Says TrendForce
- Onto Innovation’s Dragonfly® G5 System Qualified for Applications in 2.5D AI Packaging
- AI Optical Interconnect Boom Drives U.S. Firms to Expand Southeast Asia Outsourcing, Opening the Door for Cross-Industry Entrants
Latest News
- AI Drives Larger, Denser Packaging, Raising New Challenges for Equipment Makers
- Hamamatsu Photonics develops inverted emission microscope "iPHEMOS®-DDX" for failure analysis of advanced semiconductor packages
- EV Group Highlights Hybrid Bonding, Layer Transfer and Lithography Technologies for Heterogeneous Integration and Device Scaling at SEMICON West 2026
- ERS electronic Unveils Fully Automated 310 x 310mm Panel-Level Packaging System to Power AI and Chiplet Architectures
- Racyics UCIe PHY IP for GlobalFoundries 22FDX reaches silicon