Lowering the Barrier to Chiplets
Chiplets are all the rage these days, even making MIT Technology Review's 10 Breakthrough Technologies of 2024. This is pretty incredible for such a niche technology! Unfortunately, as of today chiplets are only accessible to semiconductor mega-corps. To unlock the true power of disaggregated chiplet innovation, we need to drastically reduce the barriers to chiplet based design.
One of the barriers to chiplets is the high cost and complexity of die-to-die interfaces. Existing die-to-die electrical interfaces (eg. AIB, UCIe, BoW) are designed to be simple, yet the cost of implementation (or procurement) has remained prohibitive. For chiplets to really take off, we need chiplet interfaces that are small, cheap, and fast.
To this end, we have created a low complexity (and low cost) prototype implementation of the UCIe standard, suitable for a wide range of technology nodes. The interface was designed and simulated entirely using open source EDA tools.
To read the full article, click here
Related Blogs
- Synopsys and Alchip Collaborate to Streamline the Path to Multi-die Success with Soft Chiplets
- Introduction to Chiplets: Why the Industry is Moving Beyond Monolithic Designs
- The Impact of UCIe on Chiplet Design: Lowering Barriers and Driving Innovation
- Automotive chiplets: The path towards modularity, improved cost structures and supply resilience
Latest Blogs
- Ultra-high repeatability and ultra-low insertion loss wafer and die-level visible-range E-PIC device characterization using an MPI Corp. probe system, enabled by process optimization from Quantum Transistors
- The Changing ASICs Landscape: the Shift Toward Chip Disaggregation
- Topology and Data Movement in Multi-Die Design
- How to Streamline Your Advanced Package (Chiplet, 3DIC) Interconnect Designs
- Interface IP: The Keystone for 3D Multi-Die Designs