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Embracing the Chiplet Journey

Addressing the ever-increasing compute demands of SoCs and processors

By Boyd Phelps, Senior VP and GM, Silicon Solutions Group, Cadence
Chiplet Summit 2025

Embracing the Chiplet Journey
Topics in Today s Talk
Amara s Law
Process Technology Scaling
The Problem of CPT
Packaging Advancements More Important Than Moore s Law ?
Industry Trends Driving Growth in Semiconductor TAM
Disaggregation - An Example
Impact on Cost (CapEx/OpEx) and Output
Advantage of Chiplets (Disaggregated Design)
ChatGPT: What is a Chiplet?
Traditional Abstraction Layers to Handle Complexity
Chiplets - a New Abstraction Layer
The Future of Design Automation: SoC Cockpit
Cadence Silicon Solutions Group - Enabling differentiated and constructible designs
The Cadence Chiplet Transition: TC1
System-Driven PPA Closure for 3D-IC Designs
Cadence Chiplet Focus Areas
Cadence End-to-End Approach Services for Chiplet Solutions