Sign In
English
US - English
China - 简体中文
Chiplets
Accelerator
Automotive
AI
FPGA
IO
Memory Controller & PHY
Memory
Processors
RF
Serdes
Chiplet-Ready IP
Accelerator
Automotive
AI
FPGA
IO
Memory Controller & PHY
Memory
Processors
RF
Serdes
Ecosytem
Chiplet Vendors
IP Vendors
Advanced Packaging
EDA Tool Suppliers
OSAT
Equipment
Standard
Process
Interconnect
Chiplet Integrators
Photonics
Services
Production Services
ASIC Design
Insights
Industry updates
Expert perspectives
Technical Library
Technical Papers
Videos
Slides
Wiki
AI System Connectivity for UCIe and Chiplet Interfaces Demand Escalating Bandwidth Needs
By Letizia Giuliano, VP Product Management and Marketing, Alphawave Semi
Table of Content
Outline
CHIPLETS - Ushering a New Era of Semiconductors
Metrics for Disaggregated System – Bandwidth Demand
Metrics for Disaggregated System – Power Consumption
Metrics for Disaggregated System – Latency
Metrics for Disaggregated System – Robustness
Metrics for Disaggregated System – Interoperability
Alphawave Semi UCIe Complete Solution
Alphawave UCIe PHY Support for All Package Types
System and Package Design Challenges
24Gbps Alphawave UCIe Silicon Proven in 3nm
D2D Memory Interface Evolution
HBM3E 2.5D Advanced Package Channel Analysis
Alphawave Semi High-Performance Connectivity Silicon IP
Chiplets Enabled by UCIe and Use Cases
CMN integrations – Example for IO and Memory Chiplets
Conclusions
×
Unlock this presentation
Sign In
Register for Free