Beyond Chiplets, CMOS 2.0 Moves Scaling into the Circuit

The next phase of 3D integration could depend on repartitioning circuits themselves, not just stacking finished dies or packaging larger functional blocks.

By Pat Brans, EE Times | June 17, 2026

As transistor scaling becomes harder, the semiconductor industry has been moving outward toward chiplets, advanced packaging, high-bandwidth memory, and heterogeneous integration.

CMOS 2.0, imec’s term for a new scaling paradigm, takes that movement in the opposite direction. Rather than treating advanced packaging as the endpoint of disaggregation, it pushes the idea deeper into the chip itself. The goal is to create new ways to connect logic, memory, I/O, and power delivery inside a 3D architecture.

“When we are doing CMOS 2.0, it’s of course about disaggregating the system,” Zsolt Tokei, imec fellow and program director for 3D system integration, told EE Times. “But not necessarily in the traditional way.”

To read the full article, click here