Alphawave Semi Tapes Out Breakthrough 36G UCIe™ IP on TSMC 2nm, Unlocking Foundational AI Platform IP on Nanosheet Processes
First UCIe Die-to-Die IP Subsystem on TSMC’s 2nm Process with CoWoS® Advanced Packaging Technology Delivers 11.8 Tbps/mm Bandwidth Density and a Scalable Path for 64G Die to Die Interconnects
LONDON, United Kingdom, and TORONTO, Canada – June 5th, 2025 - Alphawave Semi (LSE: AWE), a global leader in high-speed connectivity and compute silicon for the world’s technology infrastructure, announced the successful tape out of one of the industry’s first UCIe™ IP subsystem on TSMC’s N2 process, supporting 36G die-to-die data rates. The solution is fully integrated with TSMC’s Chip-on-Wafer-on-Substrate (CoWoS®) advanced packaging technology, unlocking breakthrough bandwidth density and scalability for next-generation chiplet architectures.
This milestone builds on the recent release of the Alphawave Semi AI Platform, proving readiness to support the future of disaggregated SoCs and scale-up infrastructure for hyperscale AI and HPC workloads. With this tape-out, Alphawave Semi becomes one of the industry’s first to enable UCIe connectivity on 2nm nanosheet technology, marking a major step forward for the open chiplet ecosystem.
“We’re proud to lead the industry into the N2 era with the first UCIe IP on this advanced node,” said Mohit Gupta, Senior VP & GM, Custom Silicon & IP, Alphawave Semi. “Our 36G subsystem validates a new class of high-density, power-efficient chiplet connectivity and paves the way for 64G UCIe and beyond—critical for AI and high-radix networking applications.”
Alphawave Semi’s one of the industry’s first UCIe IP subsystem on TSMC’s 2nm process delivers 36G performance with 11.8 Tbps/mm bandwidth density, ultra-low power and latency, and advanced features like live per-lane health monitoring and comprehensive testability. Compliant with UCIe 2.0 standard and supporting multi protocols, including PCIe®, CXL™, AXI, CHI and more with Alphawave Semi’s highly configurable and efficient Streaming Protocol D2D Controller.
Alphawave Semi is advancing key ecosystem collaborations to enable groundbreaking technologies, leveraging D2D-based open chiplet interoperability to drive a broader AI connectivity platform for the industry. Alphawave Semi’s UCIe IP on the TSMC N2 process affirms its position as one of the leading enablers of scalable, open chiplet ecosystems.
“Our latest collaboration with Alphawave Semi underscores our shared commitment to driving advancements in high-performance computing through design solutions that fully leverage the performance and energy-efficiency advantages of TSMC’s advanced process and packaging technologies,” said Lipen Yuan, Senior Director of Advanced Technology Business Development at TSMC. “This milestone illustrates how close collaboration with our Open Innovation Platform® (OIP) partners like Alphawave Semi can enable the quick delivery of advanced interface IP and custom silicon solutions to meet the increasing demands of AI and cloud infrastructure.”
Alphawave Semi is already executing on its plans to deliver next-generation UCIe solutions, with 64G UCIe support — empowering AI and HPC customers to lead in a rapidly evolving chiplet-driven landscape.
About Alphawave Semi
Alphawave Semi is a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure. Faced with the exponential growth of data, Alphawave Semi's technology services a critical need: enabling data to travel faster, more reliably, and with higher performance at lower power. We are a vertically integrated semiconductor company, and our IP, custom silicon, and connectivity products are deployed by global tier-one customers in datacenters, compute, networking, AI, 5G, autonomous vehicles, and storage. Founded in 2017 by an expert technical team with a proven track record in licensing semiconductor IP, our mission is to accelerate the critical data infrastructure at the heart of our digital world. To find out more about Alphawave Semi, visit: awavesemi.com.
Related Chiplet
- Optical Chiplet
- Reverse Gearbox Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
Related News
- Alphawave Semi Launches Industry’s First 3nm UCIe IP with TSMC CoWoS Packaging
- Unveiling the Availability of Industry’s First Silicon-Proven 3nm, 24Gbps UCIe™ IP Subsystem with TSMC CoWoS® Technology
- Alphawave Semi Taped-Out Industry Leading 64Gbps UCIe™ IP on TSMC 3nm for the IP Ecosystem, Unleashing Next Generation of AI Chiplet Connectivity
- Alphawave Semi Delivers Cutting-Edge UCIe™ Chiplet IP on TSMC 3DFabric® Platform
Latest News
- Amkor Technology and NVIDIA Advance Strategic Partnership for AI Infrastructure
- Siemens expands agentic AI collaboration to tackle 3D IC power and thermal challenges with NVIDIA
- Photon Bridge Raises €10M to Tackle AI’s Emerging Laser Bottleneck
- Abacus Semiconductor and Aalto University Announce Research Cooperation on High-Speed Chiplet Interconnects
- UK Launches Semiconductor Catapult to Strengthen Sovereign Capabilities in AI Hardware and Defence