AI and Chiplets Prominent at TSMC OIP 2025
By Majeed Ahmad, EETimes | September 26, 2025
The design tool offerings of the top three EDA houses showcased at TSMC’s annual U.S. event once more affirm the two defining trends in the current semiconductor landscape: artificial intelligence (AI) and chiplets. TSMC’s Open Innovation Platform (OIP) Ecosystem Forum brings together partners to demonstrate their design advancements of TSMC’s latest process nodes and packaging technologies.
The EDA trio’s announcements at the event encompass new AI flows and multi-die innovations relating to 3D IC, advanced packaging, and chiplets. The advancements in AI and chiplet realms are intertwined, paving the way for high-performance AI and HPC chips that serve compute-intensive workloads.
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related News
- Alphawave Semi and Arm to Present on Chiplets for Architecting Next-Generation Terabit AI Networks at the TSMC OIP Ecosystem Forum North America
- Lorentz Solution Jointly Presents with NVIDIA on Large-Scale 3D Terahertz EM Simulation for Real IC/3DIC Silicon Case Studies in Photonic Switches at 2025 TSMC OIP
- Teradyne Awarded 2025 TSMC Open Innovation Platform® (OIP) Partner of the Year for TSMC 3DFabric® Testing
- TSMC plans automotive chiplet process for 2025
Latest News
- Imec unlocks system-level III-V chiplet integration on Si-CMOS by advancing its 300mm RF silicon interposer platform with high-density MIMCAPs, passive modeling, and laser-assisted bonding
- CoAsia SEMI Unveils Advanced Strategy for Next-Generation Chiplet Platform 'CoCs™' at Samsung SAFE Forum
- JCET Launches Next-Generation Power Module Packaging and Test Solutions for AI Data Centers
- As Chips Go Vertical, Metrology Struggles to Keep Up
- Silicon Box Secures SGD 100M Financing to Accelerate Growth in Advanced Packaging