The Chiplet Revolution
Reducing demands on a single chip by using smaller chips dedicated to specific functions.
When Mark Kuemerle, vice president of technology at semiconductor manufacturer Marvell, needed to familiarize some new engineering hires with one of the challenges facing their industry, he borrowed a bunch of LEGO blocks from his kids. He presented the group with a select number of mismatched blocks. The pieces, Kuemerle explained to his new initiates, were meant to represent different chips with particular functions.
Traditionally, all the critical components of a semiconductor have been packaged onto a single piece of silicon, an approach called homogeneous integration. The exercise Kuemerle proposed reflected a design strategy called heterogeneous integration, which pulls together different chips, known as chiplets, with their own specific functions. These chiplets can vary not only in terms of what they are designed to do, but also in their size and specifications. A memory chip might be relatively small, for example, and one designed for machine learning tasks much larger.
Related Chiplet
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
- UCIe based 12-bit 12-Gsps Transceiver
Related Blogs
- The Chiplet Revolution
- UCIe and Automotive Electronics: Pioneering the Chiplet Revolution
- Silicon Creations is Enabling the Chiplet Revolution
- The Future of Chiplet Reliability
Latest Blogs
- Scaling AI Data Centers: The Role of Chiplets and Connectivity
- Is a GPU, ASIC or chiplet-based SoC better for AI as we switch from training to inference?
- Siemens EDA intros next-gen ESD; focus on chiplet-design kits (CDK)
- Accelerating the AI Economy through Heterogeneous Integration
- Outlook 2025: Embracing Chiplets