The Future of Chiplet Reliability
Interconnect failure prediction with 100% lane coverage
Chipmakers are increasingly turning to advanced packaging to overcome the reticle size limit of silicon manufacturing without increasing transistor density. This method also allows hybrid devices with dies in different process nodes while improving yield, which decreases exponentially with size.
However, 2.5D/3D designs introduce a fair share of new challenges, one of the most significant being poor visibility into the interconnect.
The toll of poor visibility into die-to-die (D2D) interconnects
Engineers spend months designing a chiplet, only to discover that almost no internal die pins are accessible to the test program – it's a quality nightmare. Even if the individual dies undergo thorough testing, the numerous lanes that connect them in the advanced package are often left in the dark.
Traditional testing methods based on DFT BIST offer limited relief to engineers. They are useful merely in test mode, leaving a big question mark on what might happen in real-life scenarios. Also, they only provide sample lane coverage, which may lead to oversight of critical malfunctions.
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