Silicon Creations is Enabling the Chiplet Revolution

By Mike Gianfagna

June 5, 2024

The multi-die chiplet-based revolution is upon us. The ecosystem will need to develop various standards and enabling IP to make the “mix and max” concept a reality. UCIe, or Universal Chip Interconnect express is an open, multi-protocol on-package die-to-die interconnect and protocol standard that promises to pave the way to a multi-vendor chiplet market. But delivering an implementation that balances all the requirements for power, performance and form factor can be quite challenging. At the recent IP-SoC Silicon Valley event, Silicon Creations presented a comprehensive strategy to overcome these challenges. Read on to see how Silicon Creations is enabling the chiplet revolution.

About Silicon Creations

Silicon Creations is a self-funded, leading silicon IP provider with development in the US and Poland, and a sales presence worldwide. The company provides world-class IP for precision and general-purpose timing (PLLs), oscillators, low-power, high-performance multi-protocol and targeted SerDes, and high-speed differential I/Os. Applications include smart phones, wearables, consumer devices, processors, network devices, automotive, IoT, and medical devices.

The majority of the world’s top 50 IC companies work with Silicon Creations. 1,000+ chips contain the company’s IP using over 700 unique IP products. Silicon Creations touches over 150 production tape-outs each year with over 400 customers, with 3nm designs in mass production. You can learn more about Silicon Creations at SemiWiki here.

About the Die-to-Die Interface Challenges

Blake Gray developed a comprehensive presentation for IP-SoC Silicon Valley. He is the Director of Hardware Engineering at Silicon Creations. He’s been with the company for over 12 years. Unfortunately, he fell ill before the event and Jeff Galloway, Principal and Co-Founder at Silicon Creations stepped in to present for Blake. Let’s take a look at the excellent material Blake developed. It begins with a discussion of the design and performance challenges of transmit (TX) clock design.