Zero ASIC Chiplets

Filter

4 Chiplet (1 - 4)

Active silicon interposer integrating networking functionality, 3D CLINK chiplet interfaces, and 2D UCIe chiplet interfaces
- Network-On-Interposer
- 4 Tbps aggregate bisection bandwidth
Quad-core 64-bit RISC-V ISA, dual-issue, in-order application class processor chiplet implemented in 12nm
Heterogeneous FPGA chiplet implemented in 12nm
- 5K LUTs
- 16 x 8KB SRAMs (1Mb)
- 16 DSP blocks
Machine learning accelerator chiplet implemented in 12nm
- 3 TOPS peak performance AI accelerator
- Hardware accelerated ReLU/Softmax nonlinearities
- Hardware accelerated transpose