The chiplet universe is coming: What’s in it for you?
By Guillaume Boillet, Arteris
EDN (February 21, 2024)
There’s a lot of talk and excitement about chiplets these days, but there’s also a lot of confusion. What is available today? What should I expect in terms of interoperability? Is the promise of an emerging ecosystem real? More fundamentally, developers of high-end systems-on-chip (SoCs) need to consider a central question: “What’s in it for me?” The answer, unsurprisingly, varies depending on the type of application and the target market for these devices.
For the last few years, I have been closely monitoring the multi-die market, and I’ve been talking to a wide variety of players ranging from chip designers to chip manufacturers to end users of our system IP product offering. Although commentators and stakeholders accurately describe key benefits of chiplet technology, I’ve observed that these descriptions are rarely comprehensive and often lack structure.
As a result, I felt the need to identify common themes, reflect on their importance for future deployment and map them on the key industry verticals. This blog aims to summarize these insights in a diagram, with the hope that it is useful to you.
To read the full article, click here
Related Chiplet
- Automotive AI Accelerator
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
Related Technical Papers
- The Revolution of Chiplet Technology in Automotive Electronics and Its Impact on the Supply Chain
- Why Chiplet-Based Architecture Is the Next Frontier in Semiconductors
- Probeless Fault Isolation Capability for 2.5D/3D Chiplet Die-to-Die Interconnect
- What’s Next for Multi-Die Systems in 2024?
Latest Technical Papers
- Building Advanced 3D Devices with DBI®
- PPAC Driven Multi-die and Multi-technology Floorplanning
- Taking 3D IC Heterogeneous Integration Mainstream
- CATCH: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems
- Three-dimensional photonic integration for ultra-low-energy, high-bandwidth interchip data links