SPIRAL: Signal-Power Integrity Co-Analysis for High-Speed Inter-Chiplet Serial Links Validation
By Xiao Dong1, Songyu Sun1, Yangfan Jiang1, Jingtong Hu2, Dawei Gao1,3, Cheng Zhuo1,4
1Zhejiang University, Hangzhou, China
2University of Pittsburgh, Pittsburgh, USA
3Zhejiang ICsprout Semiconductor Co., Ltd., Hangzhou, China
4Key Laboratory of Collaborative Sensing and Autonomous Unmanned Systems of Zhejiang Province, Hangzhou, China
Chiplet has recently emerged as a promising solution to achieving further performance improvements by breaking down complex processors into modular components and communicating through high-speed inter-chiplet serial links. However, the ever-growing on-package routing density and data rates of such serial links inevitably lead to more complex and worse signal and power integrity issues than a large monolithic chip. This highly demands efficient analysis and validation tools to support robust design. In this paper, a signal-power integrity co-analysis framework for high-speed inter-chiplet serial links validation named SPIRAL is proposed. The framework first builds equivalent models for the links with a machine learning-based transmitter model and an impulse response based model for the channel and receiver. Then, the signal-power integrity is co-analyzed with a pulse response based method using the equivalent models. Experimental results show that SPIRAL yields eye diagrams with 0.82--1.85% mean relative error, while achieving 18--44× speedup compared to a commercial SPICE.
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