Chiplets Make Progress Using Interconnects As Glue
By Ann Mutschler, SemiEngineering (October 31st, 2024)
Industry learning expands as more SoCs are disaggregated at leading edge, opening door to more third-party chiplets.
Breaking up SoCs into their component parts and putting those and other pieces together in some type of heterogeneous assembly is beginning to take shape, fueled by advances in interconnects, complex partitioning, and industry learnings about what works and what doesn’t.
While the vision of plug-and-play remains intact, getting there is a lot more complicated than initially imagined. It can vary greatly by application and by workload, which in turn can affect timing, latency, and cost. And it can vary by package type, whether AI is included or not, how much software is needed for scheduling and prioritization, and the type of interconnects being used.
To read the full article, click here
Related Chiplet
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
- UCIe based 12-bit 12-Gsps Transceiver
Related News
- Chiplets diary: Three anecdotes recount design progress
- Chiplets Make Case for More Apps
- How do UCIe and BoW interconnects support generative AI on chiplets?
- How does UCIe on chiplets enable optical interconnects in data centers?
Latest News
- Test & Yield Challenges of Chiplet-Based Semiconductor Products
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- Silicon Box welcomes European Commission approval of €1.3 billion Italian State aid measure to support new advanced packaging facility in Novara
- Fraunhofer IMS Takes a Key Role in Establishing the APECS Pilot Line
- EdgeCortix Joins AI-RAN Alliance to Accelerate the Integration of AI and Next-gen RAN Infrastructure