Chiplets Make Progress Using Interconnects As Glue
By Ann Mutschler, SemiEngineering (October 31st, 2024)
Industry learning expands as more SoCs are disaggregated at leading edge, opening door to more third-party chiplets.
Breaking up SoCs into their component parts and putting those and other pieces together in some type of heterogeneous assembly is beginning to take shape, fueled by advances in interconnects, complex partitioning, and industry learnings about what works and what doesn’t.
While the vision of plug-and-play remains intact, getting there is a lot more complicated than initially imagined. It can vary greatly by application and by workload, which in turn can affect timing, latency, and cost. And it can vary by package type, whether AI is included or not, how much software is needed for scheduling and prioritization, and the type of interconnects being used.
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- Chiplets diary: Three anecdotes recount design progress
- Chiplets Make Case for More Apps
- How do UCIe and BoW interconnects support generative AI on chiplets?
- How does UCIe on chiplets enable optical interconnects in data centers?
Latest News
- Socionext and imec Update Core Partner Program
- TCS Unveils Chiplet-Based System Engineering Services to Accelerate Semiconductor Innovation
- Deca and Silicon Storage Technology Announce Strategic Collaboration to Enable NVM Chiplet Solutions
- Lam Research Introduces VECTOR® TEOS 3D to Address Critical Advanced Packaging Challenges in Chipmaking
- Scintil Photonics Raises $58M to Scale Integrated Photonics for AI Factories