How do UCIe and BoW interconnects support generative AI on chiplets?
By Jeff Shepard, Microcontroller Tips (February 28, 2024)
The bunch-of-wires (BoW) and Universal Chiplet Interconnect Express (UCIe) standards provide designers with tradeoffs in terms of throughput, interconnect density, delay, and bump pitch. This FAQ compares the performance of BoW and UCIe and looks at how optical interconnects may provide a path to even higher performance interconnects in chiplets.
To realize optimal performance for generative artificial intelligence (AI), machine learning (ML), and other high-performance computing (HPC) applications, designers are turning to chipsets that can combine AI accelerators, GPUs, CPU, memory, and networking in a single package. Interconnecting heterogeneous devices in a chiplet can be especially challenging.
To read the full article, click here
Related Chiplet
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
- UCIe based 12-bit 12-Gsps Transceiver
Related News
- How can in-package optical interconnects enhance chiplet generative AI performance?
- How does UCIe on chiplets enable optical interconnects in data centers?
- Alphawave Semi to Reveal Ecosystem and Key Architectures Unlocking Generative AI Potential at EE Times' "Chiplets: Building the Future of SoCs" Seminar
- Why UCIe is Key to Connectivity for Next-Gen AI Chiplets
Latest News
- How AI Will Define the Next Silicon Supercycle
- Baya Systems Revolutionizes AI Scale-Up and Scale-Out with NeuraScale™ Fabric
- Axelera AI Secures up to €61.6 Million Grant to Develop Scalable AI Chiplet for High-Performance Computing
- Chiplets: A Technology, Not A Market
- Enosemi and Jabil to develop advanced packaging process technology for photonic chips