3D IC Design Ecosystem Panel at #61DAC
At #61DAC our very own Daniel Nenni from SemiWiki moderated an informative panel discussion on the topic of 3D IC Design Ecosystem. Panelists included: Deepak Kulkarni – AMD, Lalitha Immaneni – Intel Foundry, Trupti Deshpande – Qualcomm, Rob Aitken – CHIPS, Puneet Gupta – UCLA, Dragomir Milojevic – imec. Each panelist had a brief opening statement, then Daniel guided them through a series of questions, so I’ll paraphrase what I learned.
Deepak Kulkarni, AMD – there are big challenges in AI and the data centers caused by power consumption, because it’s taking megawatts to train a model with a trillion parameters over 30 days, and power projections of 100MW to train 100 trillion parameters.
For 3.5D packaging the motivation is improved power efficiency, where 3D Hybrid bonding has the densest and most power-efficient chiplet interconnect. Using 2.5D helps package HBM and compute together, and the goal is better system-level efficiency.
To read the full article, click here
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