Revamping the Semiconductor Industry with Hybrid Bonding
By Laura Mirkarimi, Adeia
EETimes (September 20, 2024)
Hybrid bonding, also known as direct-bond interconnect, is poised to transform a semiconductor industry wrestling with Moore’s Law slowing as market demands for ubiquitous access to more data rise. While the industry turned to advanced packaging solutions in this More-than-Moore Era, there is an emerging consensus that the limits of conventional packaging technology may well have been reached. This stark realization has put a growing community of scientists and engineers on a quest to identify and deploy technologies that allow for a higher density of interconnects than traditional copper microbumps.
Hybrid bonding meets this requirement by reducing the interconnect size, enabling more efficient and faster signal transmission. The technology has roots in research from the late 2000s to early 2010s. Significant advancements have taken place over the past few years, as companies and research institutions, largely led by Adeia, develop and refine techniques to address the growing demand for higher performance, greater interconnect density and improved thermal management in semiconductor devices.
Hybrid-bonding attributes
Among the many attributes driving interest in—and adoption of—hybrid bonding is its ability to allow chips from different nodes, functions and manufacturers to be assembled heterogeneously while behaving as if monolithically built. The concept of designing chiplets—small portions of functionality in silicon—and connecting them with standard interfaces has created a revolution in the industry.
Related Chiplet
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
- UCIe based 12-bit 12-Gsps Transceiver
Related Technical Papers
- The Next Frontier in Semiconductor Innovation: Chiplets and the Rise of 3D-ICs
- Securing the new chiplet era of semiconductor design
- Intel Delivers Cutting-Edge Process Technologies to the Data Center with Intel 18A and Advanced Chiplet Packaging
- 3D Integration, Advanced Metrology Shape the Semiconductor Landscape
Latest Technical Papers
- Spiking Transformer Hardware Accelerators in 3D Integration
- GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package
- AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration
- Chiplever: Towards Effortless Extension of Chiplet-based System for FHE
- The Survey of Chiplet-based Integrated Architecture: An EDA perspective