Probeless Fault Isolation Capability for 2.5D/3D Chiplet Die-to-Die Interconnect

By Terrence Tan, Senior Director, Silicon, Manufacturing and Packaging Engineering, Microsoft Penang, Malaysia 

Abstract:

Chiplet-based designs are essential for various applications, such as Data Center, AI, Client, and Automotive. Die-to-Die (D2D) interconnects are needed for all 2.5D and 3D packaging, and they are prone to failure, even with interconnect redundancy, because of their large number and close spacing. To ensure high yield, we need a fast way to diagnose any failure that occurs in the D2D interconnects during manufacturing or infield. Physical failure analysis is more difficult in the advanced packaging era, and it faces significant technical challenges, takes a lot of time and is costly. This paper presents a probeless fault isolation method that enables fault isolation of D2D interconnects during production test and/or in-field without using physical failure analysis equipment. This novel approach accelerates volume diagnosis from D2D interconnect failure because this feature is inline, and the production test has the required data about which chiplet interconnect is faulty and fault types. It also provides quick feedback for assembly and defect isolation as this architecture does not require complex SOC bring up. This new capability can be run periodically in the field and can be part of an ongoing industry standardization for chiplet and interconnect debuggability in high volume production situations.

Keywords:

probeless fault isolation, production volume diagnosis, in-field diagnosis

I. INTRODUCTION

Die-to-die (D2D) interconnect is an essential component for the development of advanced packaging that uses 2.5D and 3D chiplet integration technology. There are various types of die-to-die interconnect topologies and protocols in the industry to meet the demand for higher interconnect bandwidth. Some examples of industry topologies are 2.5D, 3D and Silicon Bridges and some examples of industry protocols are HBM (High Bandwidth Memory), BOW (Bunch Of Wires), AIB (Advance Interface Bus) and UCIE (Universal Chiplet Interconnect Express). Chiplets are integrated on an interposer and connected by the suitable dieto-die topologies and protocols.

As we stack different chiplets on an interposer and connect them together as shown in Figure 1, we can expect to see failures caused by the assembly process. One common thing across different D2D topologies and protocols is the need for a high-volume manufacturing test to screen out the failures that result from interconnect defects. It is important to have a fast yield learning and feedback loop to inform the package assembly team about the reliability of the interconnect. While the die-to-die interconnect shown in Figure 1 has a robust Design for Test (DFT) to enable high production test coverage [1], the DFT capability has limitation on fault isolation of interconnect failure during production test. How can we effectively and quickly identify the root cause of D2D test failure/yield issue in production due to assembly or actual D2D circuitry issue?

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