Universal Chiplet Interconnect Express: An Open Industry Standard for Memory and Storage Applications
By Debendra Das Sharma (CXL Board Technical Task Force, Intel), Thomas Coughlin (Coughlin Associates)
Abstract
Continuing advances in computing will require chiplets connected by the Universal Chiplet Interconnect Express (UCIe) to create cost-effective high-performance customized applications and new memory hierarchies. The optical UCIe can expand this functionality to the pod and rack level.
There are many drivers for on-package integration of chiplets. Overcoming reticle limitations to deliver performance, functionality, and yield tradeoffs with larger dies is a primary reason why today volume CPUs and GPUs use chiplet-based solutions with proprietary scale-up interconnects. Chiplet approaches reduce the compromises required with monolithic designs. Lowering the overall portfolio cost with a time-to-market advantage is another motivation for deploying chiplets.
To read the full article, click here
Related Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Interconnect Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Technical Papers
- High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions
- FoldedHexaTorus: An Inter-Chiplet Interconnect Topology for Chiplet-based Systems using Organic and Glass Substrates
- Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging
- Fault Modeling, Testing, and Repair for Chiplet Interconnects
Latest Technical Papers
- AuxiliarySRAM: Exploring Elastic On-Chip Memory in 2.5D Chiplet Systems Design
- System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution
- Material-Mechanistic Interplay in SiCN Wafer Bonding for 3D Integration
- Fault Modeling, Testing, and Repair for Chiplet Interconnects
- Low-Loss Integration of High-Density Polymer Waveguides with Silicon Photonics for Co-Packaged Optics