On hardware security and trust for chiplet-based 2.5D and 3D ICs: Challenges and Innovations

By Juan Suzano (1, 2, 3) , Fady Abouzeid (1) , Giorgio Di Natale (3) , Anthony Philippe (4) , Philippe Roche  (1)
1 ST-CROLLES - STMicroelectronics [Crolles]
2 DSCIN - Département Systèmes et Circuits Intégrés Numériques
3 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
4 LSTA - Laboratoire Systèmes-sur-puce et Technologies Avancées

The relentless pace of transistor miniaturization has enabled developers to continuously increase chip complexity since the beginning of the information age. However, as transistors get smaller and chips become larger, the cost of manufacturing ICs becomes increasingly prohibitive. As Moore's Law is coming to an end, industry and academia have been exploring new paradigms to keep up with the ever-increasing demand for performance and functionality while dealing with the constraints of power consumption, area, and yield constraints. In this context, 3DICs are considered the future of the IC industry as they enable designers to fulfill both the "More Moore" and the "More than Moore" paradigm. A key feature of the 3DIC is that it can be manufactured by assembling multiple chiplets. Chiplets are single-purpose dies that must be assembled with other chiplets to form a complete system. Researchers and industry leaders believe that a chiplet market will form and that products with off-the-shelf chiplets will emerge. This scenario offers many economic opportunities. However, it also raises concerns regarding the security and trust (S&T) of chiplet-based designs. Malicious chiplets, Hardware trojans, and chiplet intellectual property theft are threats that must be addressed as the industry moves towards the "chiplet age". In this survey, we introduce the different types of 3DICs and their production chain. We then define the threats that threaten the different steps of the 3DIC manufacturing process. Finally, we present and discuss the state of the art in hardware S&T techniques for chiplet-based 3DICs.

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