Multi-Die Systems Reshape Semiconductor Innovation
By Shekhar Kapoor, Synopsys
ElectronicDesign (Oct. 3, 2023)
Demands have never been higher for—and on—semiconductors. From smart speakers to self-driving cars and robotic manufacturing equipment, chips are elevating our smart everything world to new heights. In 2021, the semiconductor industry marked a record by shipping 1.15 trillion chips. Increasingly, as applications become more intelligent, these chips are being asked to deliver much more processing prowess, better power efficiency, and, for space-constrained designs, smaller footprints.
It’s a promising and exciting time for the electronics industry, with transformer models, generative artificial intelligence (AI), and immersive experiences creating unprecedented demand for compute and data rates at ever lower power levels. As a result, new players are entering the chipmaking landscape and bringing to life innovations that are transforming the way we learn, work, play, and, when you think about it, live.
However, all of these chipmakers are facing deep limitations as Moore’s Law slows, particularly for designs targeting compute-intensive workloads.
The reality is, migrating traditional, monolithic semiconductor designs to smaller process nodes is no longer generating the benefits that such scaling once did. And attempting to do so will even hit manufacturing walls.
To read the full article, click here
Related Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Interconnect Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Technical Papers
- What’s Next for Multi-Die Systems in 2024?
- The Next Frontier in Semiconductor Innovation: Chiplets and the Rise of 3D-ICs
- NoCs and the transition to multi-die systems using chiplets
- Complex Heterogeneous Integration Drives Innovation In Semiconductor Test
Latest Technical Papers
- AuxiliarySRAM: Exploring Elastic On-Chip Memory in 2.5D Chiplet Systems Design
- System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution
- Material-Mechanistic Interplay in SiCN Wafer Bonding for 3D Integration
- Fault Modeling, Testing, and Repair for Chiplet Interconnects
- Low-Loss Integration of High-Density Polymer Waveguides with Silicon Photonics for Co-Packaged Optics