Garblet: Multi-party Computation for Protecting Chiplet-based Systems

By Mohammad Hashemi, Shahin Tajik and Fatameh Ganji | Worcester Polytechnic Institute, Worcester, USA

Abstract.

The introduction of shared computation architectures assembled from heterogeneous chiplets introduces new security threats. Due to the shared logical and physical resources, an untrusted chiplet can act maliciously to surreptitiously probe the data communication between chiplets or sense the computation shared between them. This paper presents Garblet, the first framework to leverage the flexibility offered by chiplet technology and Garbled Circuits (GC)-based MPC to enable efficient, secure computation even in the presence of potentially compromised chiplets. Our approach integrates a customized hardware Oblivious Transfer (OT) module and an optimized evaluator engine into chiplet-based platforms. This configuration distributes the tasks of garbling and evaluating circuits across two chiplets, reducing communication costs and enhancing computation speed. We implement this framework on an AMD/Xilinx UltraScale+ multi-chip module and demonstrate its effectiveness using benchmark functions. Additionally, we introduce a novel circuit decomposition technique that allows for parallel processing across multiple chiplets to further improve computational efficiency. Our results highlight the potential of chiplet systems for accelerating GC (e.g., the time complexity of garbled AES is 0.0226ms) in order to guarantee the security and privacy of the computation on chiplets.

Keywords: Multiparty computation , Garbled circuits Oblivious transfer, Chiplet, Heterogeneous Integration

1. Introduction

There is a significant shift in the chip industry from large, monolithic chip fabrication to modular architectures built from heterogeneous chiplets. Chiplets are designed as a response to the need for high performance and maximum efficiency while attempting to manage costs associated with manufacturing and yield. These heterogeneous designs also offer advantages for combining chiplets, fabricated potentially with older technologies by a trusted facility, with ones built with cutting-edge technologies with no security features. In such cases, while the slower trusted chiplet can act as the root of trust, computationally heavy tasks can be distributed among the faster cutting-edge chiplets.

However, such multi-chip modules create some novel security risks. Since chiplets could be manufactured by various suppliers or programmed by different designers, they could act maliciously and threaten the security and privacy of computation running on them, see Fig 1. Even if all chiplets are trusted, the interposer connecting them together could act maliciously and intercept the communication between multiple chiplets.

Hence, we ask the following research question: In a highly adversarial environment, where virtually all chiplets or interposers can act maliciously, is it still possible to perform distributed computation securely? This is answered positively by secure multiparty computation (MPC), particularly Yao’s Garbled Circuits (GC), which enables parties to jointly evaluate functions without exposing underlying secret data. GCs allow two parties (the garbler and the evaluator) to jointly compute a function over their private inputs while keeping these inputs hidden from each other [BHR12]. Compared to other approaches to secure computation, namely fully homomorphic encryption (FHE), GC incurs much lower computation complexity, although at the cost of communication complexity [BCM+19].

In fact, communication can be a bottleneck for traditional GC use cases on untrusted cloud servers. The communication cost involves (1) the cost of exchanging inputs between the users and (2) the cost of running the primitive responsible for obliviously sending these inputs [CPS14]. The communication cost can be especially significant when the circuit is large. In such scenarios, the communication bandwidth is a key determinant.  In this regard, two implementation paradigms have been identified: (1) sequentially transmitting the garbled tables’ inputs, and (2) transmitting the entire circuit to be evaluated without revealing anything but the output [BELO16]. In the case of classical server communications, the former matches communication characteristics over a local area network (LAN), while the latter can be conducted much faster over a wide-area network (WAN). However, the communication inside a chip, has not been discussed in the MPC-related literature. In fact, chiplet-based systems enable high-speed, low-latency communication between individual chiplets [Xila], making them ideal for enhancing the performance of secure computations, particularly GC.

In this regard, our paper’s contributions are as follows. (1) For the first time, our paper demonstrates the feasibility of GC implementation on chiplets, enabling secure MPC even in the presence of distrustful/corrupted chiplets. Our framework, Garblet, showcases a great deal of overhead reduction compared to conventional server-client MPC. This is thanks to our chiplet-based implementation of oblivious communication as well as the flexibility offered by chiplet-based systems. In addition to minimizing communication overhead, Garblet addresses the scalability challenges commonly encountered in secure computation. Through a novel circuit decomposition technique, Garblet distributes computation tasks across multiple chiplets to enable parallel execution and, consequently, significantly reduces computation time. Another key advantage of Garblet is its ability to enhance security through hardware-level isolation. Security-critical tasks, such as encryption, can be physically separated from nonsensitive operations, limiting the potential impact of an attack on non-critical components.

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