Towards efficient ESD protection strategies for advanced 3D systems-on-chip
Guidelines for protecting the internal I/O interfaces from electrostatic discharge during die or wafer bonding steps
By Shane (Shih-Hsiang) Lin, Marko Simicic - imec
ESD protection strategies for monolithic systems-on-chip
Failures caused by electrostatic discharges (ESD) are an ongoing concern for the semiconductor industry. ESD events can affect electronic products at any point during manufacturing and assembly, and during transportation and use of the product. ESD discharges happen in a very short timeframe (pulse widths ranging from below 1ns to 200ns, and rise times from below 200ps to 10ns). In this short period of time, excess currents in the order of 0.1 – 10A might run through the IC and package, damaging the chip by causing metal interconnect burnout or gate oxide breakdown.
Not surprisingly, the industry is heavily committed to safeguard electronic products, focusing on both prevention and protection. To prevent ESD events as much as possible, IC manufacturing and assembly happen in ESD-controlled facilities, where appropriate materials are being used, and operators and equipment are properly grounded. Prevention is complemented by adding on-chip protection circuitry. These circuits shield the chip’s input and output interfaces (I/O) that connect the chip to the outside world. When an ESD event hits the chip, these circuits ensure a safe, low-resistive discharge path to the ground, while limiting voltages to a safe level.
For monolithic systems-on-chip, ESD design strategies are clearly defined and evolve with every new technology that enters the technology roadmap [1]. To qualify the chip’s robustness to ESD events, the semiconductor industry uses two ESD control standards, that are representative of the most common ESD events: the human body model (HBM) and the charged device model (CDM). While HBM represents the discharge from a human being (and, by extension, from other external objects) to an IC, CDM captures what happens when the chip itself is charged and discharges to the environment. The industry also sets ESD target levels for various electronic products. Today, monolithic systems-on-chip used in high-performance computing applications are qualified for 125V or 250V CDM, depending on customer demands. For HBM, the specs range between 100V and 500V, depending on the functionality of the I/O pins and customer demands.
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