Data Routing In Heterogeneous Chip Designs
Ensuring data gets to where it's supposed to go at exactly the right time is a growing challenge for design engineers and architects developing heterogeneous systems. There is more data moving around these chips with dozens of targets, which makes routing signals much more complicated. Ronen Perets, senior product marketing manager at Cadence Design Systems, talks with Semiconductor Engineering about some of the new problems engineers are likely to encounter with multi-vendor chiplets, what can happen when communication is not consistent, and the impact of multiple communications links between each routing node.
Related Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Interconnect Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Videos
- Analyzing Packet Data Flow in Chiplet Based SoCs
- Blue Cheetah BlueLynx for Heterogeneous Integration: 16 Gbps Chiplet Interconnect IP for UCIe & BoW
- Revolutionizing System Design: Impact of Chiplets and Heterogeneous Integration on AI Server
- Impact of Chiplets, Heterogeneous Integration and Modularity on AI and HPC systems
Latest Videos
- Optical Connectivity At 224 Gbps
- Proximity is all You Need – Two Tricks for Chiplet Interconnects
- 3D IC Podcast | The future of 3D ICs: How advanced packaging is changing the industry
- Mick Posner talks about the importance of UCIe
- Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP