Monolithic 3D: Stacking Without Chiplets
By Dr. Ian Cutress, TechTechPotato
Chiplets aren't the only way forward in chip design. This deep dive explores an alternative that starts with layered logic — distributing circuits across tiers from the outset, not just stacking components after the fact. It begins in FPGAs at Georgia Tech, but the implications reach far beyond.
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Videos
- 3D Integration is Redefining the Semiconductor Landscape: MonolithIC 3D's Zvi Or-Bach
- The UCIe™ 1.1 Specification: Future Applications of Chiplets
- Thermal Comparison between Monolithic and Chiplet ASIC Design
- IBM Research: Benefits and challenges of Chiplets
Latest Videos
- Accelerate 3D IC designs with Innovator3D IC
- On Package Memory with Universal Chiplet Interconnect Express (UCIe): A Low-Power, High-Bandwith, Low-Latency and Low-Cost Approach
- Breaking down 50 million pins: A smarter way to design 3D IC packages
- Optimizing Data Movement in SoCs and Advanced Packages
- Cache Coherency in Heterogeneous Systems