Analyzing Packet Data Flow in Chiplet Based SoCs
By Honnappa Nagarahalli, Arm
CPU vendors have introduced chiplet based SoCs with several advantages. The chiplets within the SoCs are connected together with additional interconnects. These additional interconnects introduce additional latencies compared to monolithic SoCs. This session analyses the packet flow in a typical chiplet based SoC while using DPDK. It identifies the flows where the latencies are introduced. It will introduce solutions based on the features in Arm products implemented based on industry standards.
Related Chiplet
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
Related Videos
- Paving the Road Ahead: RISC-V and Chiplet Technologies in Modern Automotive and Data Center Architectures
- Optimizing Data Movement in SoCs and Advanced Packages
- UCIe Based Chiplet Ecosystem Interoperable Testbench for Multi Vendor IP Integration
- Charting Architectural Innovation in the Chiplet Era with OCP's Cliff Grossner
Latest Videos
- Zero trust in silicon: The new security imperative for chiplet-based 3D ICs
- Beyond the data pipe: Why connectivity IP is now the system-critical layer in every 3D IC
- An Automated Interconnect Modeling Framework for Rapid Cryptolet Design Space Exploration
- DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation
- The Evolution Of UCIe