Top-Down Vs. Bottom-Up Chiplet Design
Third party chiplets are hitting the market as chiplet models evolve. Who’s calling the shots isn’t clear yet.
By Ann Mutschler, Semiconductor Engineering (November 26th, 2024)
Chiplets are gaining widespread attention across the semiconductor industry, but for this approach to really take off commercially it will require more standards, better modeling technologies and methodologies, and a hefty amount of investment and experimentation.
The case for chiplets is well understood. They can speed up time to market with consistent results, at whatever process node works best for a particular workload or application, and often with better yield than a large, monolithic SoC. But there is an underlying tug-of-war underway between large, vertically integrated players that want to tightly define the socket specifications for chiplets, and a broad swath of startups, systems companies, and government agencies pushing a top-down approach that allows chiplet developers to explore new and different options based on standardized interconnects.
To read the full article, click here
Related Chiplet
- Automotive AI Accelerator
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
Related News
- System-level UCIe IP for early architecture analysis of 3D Chiplet Design and Packaging
- Baya Systems and Blue Cheetah Partner to Deliver Chiplet Interconnect Solutions
- OPENEDGES Unveils UCIe Chiplet Controller IP, Expanding Design Portfolio
- Interconnect underdogs steering chiplet design bandwagon
Latest News
- Three-Way Race To 3D-ICs
- Promex Industries Expands Best-in-Class Capabilities, Installing Laser Depaneling and Advanced SPI Systems on Manufacturing Line
- Cyber Threats Multiply With Commercial Chiplets
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- Intel Foundry Gathers Customers and Partners, Outlines Priorities