Outlook 2025: Embracing the chiplet journey

Meeting the challenge of larger, more complex SoCs to address today’s ever-increasing computing demands.

By Boyd Phelps, Senior Vice President and General Manager, Silicon Solutions Group, Cadence

Modern system-on-chip (SoC) design architectures are evolving rapidly, driven by a variety of factors. Traditional SoC design methodology partitions key design components into proprietary, differentiated accelerators or cores alongside reusable, standards-based IP components and subsystems. Until recently, SoC designs were implemented as monolithic designs with all design elements - both proprietary and licensed- integrated into a single piece of silicon. Today, this monolithic approach is evolving to a more disaggregated, or ‘sum of chiplets’, approach.

This evolution is facilitated by several developments that have helped address the challenges of increasingly complex SoCs. Monolithic silicon approaches now often bump up against silicon manufacturing reticle limits, outstripping the capabilities of Moore’s Law scaling. In addition, advanced-node silicon takes far longer to reach mature yields and requires longer design cycles. Not only are wafer manufacturing cycles getting longer, but intrinsic silicon wafer costs are increasing and the rising cost per transistor (CPT) has begun to outweigh the benefits of technology scaling that historically have come with advancements in process technology. Today’s SoC designers must be far more judicious in deciding which design elements to move to the next node and which to maintain in older nodes to achieve a more scalable cost and development framework.

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