Signal Integrity Plays Increasingly Critical Role In Chiplet Design
Chiplet design engineers have complex new considerations compared to PCB concepts.
By Ann Mutschler, SemiEngineering (February 13th, 2025)
Maintaining the quality and reliability of electrical signals as they travel through interconnects is proving to be much more challenging with chiplets and advanced packaging than in monolithic SoCs and PCBs.
Signal integrity is a fundamental requirement for all chips and systems, but it becomes more difficult with chiplets due to reflections, loss, crosstalk, process variation, and various types of noise and physical effects. Electrical signals need to arrive at their destination at the right time, waveform shape, and with consistent voltage levels. This was hard enough in monolithic chips, but it takes on a whole new dimension in advanced packages.
To read the full article, click here
Related Chiplet
- Automotive AI Accelerator
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
Related News
- Chiplet Interconnects Add Power And Signal Integrity Issues
- Signal Integrity Designs at Organic Interposer CoWoS-R for HBM3-9.2Gbps High Speed Interconnection of 2.5D-IC Chiplets Integration
- System-level UCIe IP for early architecture analysis of 3D Chiplet Design and Packaging
- Baya Systems and Blue Cheetah Partner to Deliver Chiplet Interconnect Solutions
Latest News
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
- NHIZ promotes chiplet industry's development and cooperation
- Cadence and TSMC Advance AI and 3D-IC Chip Design with Certified Design Solutions for TSMC’s A16 and N2P Process Technologies
- Breaking the Memory Wall: How d-Matrix Is Redefining AI Inference with Chiplets
- Alphawave Semi Delivers Foundational AI Platform IP for Scale-Up and Scale-Out Networks