When Standards Enable Chiplets
Nobody wants standards until the lack of them inhibits the development of the solutions that they need. That is often too late.
By Brian Bailey, Semi Engineering | July 30th, 2025
Semiconductor Engineering sat down and discussed the need for standards to enable an ecosystem for chiplets with Mark Kuemerle, vice president of technology for Marvell; Letizia Giuliano, vice president for product marketing and management at Alphawave Semi; Hee-Soo Lee, HSD segment lead for Keysight; Mick Posner, senior product group director for Cadence’s Compute Solutions Group; and Rob Kruger, product management director for Synopsys’ multi-die strategy solutions group. What follows are excerpts from a roundtable discussion held at this year’s Design Automation Conference.
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- What are the challenges when testing chiplets?
- How does UCIe on chiplets enable optical interconnects in data centers?
- ASE’s VIPack™ Enables Innovational AI Devices Through Advanced Interconnect Technology for Chiplets
- Faraday Unveils 2.5D/3D Advanced Package Service for Chiplets
Latest News
- Celestial AI Introduces Photonic Fabric™ Module - World’s First SoC with In-Die Optical Interconnect, Ushering in a New Era of Interconnects
- Amkor Announces New Site for U.S. Semiconductor Advanced Packaging and Test Facility
- Arteris Joins UALink Consortium to Accelerate High-Performance AI Networks Scale Up
- Athos Silicon Chief mSoC™ Architect Francois Piednoel to Present the IEEE World Technology Summit 2025 in Berlin
- Marvell Unveils Industry’s First 64 Gbps/wire Bi-Directional Die-to-Die Interface IP in 2nm to Power Next Generation XPUs