Does This Chip Hold the Future of the Semiconductor Industry?
By James Morra, Electronic Design (April 3, 2024)
Learn more about Pike Creek and its potential implications as the first test chip featuring chiplets linked by the UCIe standard.
Today, the movers and shakers of the semiconductor industry are no longer putting all of their transistors in one chip. Instead, they’re pulling apart their largest, most advanced chips into smaller silicon die referred to as chiplets. These can be made on the best process technology for the job and then repackaged to mimic a single monolithic system-on-chip (SoC). By integrating the heterogeneous die in a single package, such “multi-die” systems bring more performance to the table for everything from AI to RF.
For now, these companies can mix and match chiplets made by different foundries, based on varying process nodes, and then bind them all together in a system-in-package (SiP) with any type of advanced packaging. But bringing third-party chiplets into the package poses a challenge, largely due to the lack of a standard die-to-die connection. In that context, the biggest names in the chip business are hoping to fill the gap with a new standard, ushering in a new era of domain-specific accelerators in the process.
Related Chiplet
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
- UCIe based 12-bit 12-Gsps Transceiver
Related News
- Keysight Introduces Chiplet PHY Designer for Simulating D2D to D2D PHY IP Supporting the UCIe™ Standard
- Eliyan Supports Latest Version of UCIe Chiplet Interconnect Standard, Continues to Drive Performance and Bandwidth Capabilities to 40Gbps and Beyond to Help Meet the Needs of the Multi-die Era
- Eliyan Sets New Standard for Chiplet Interconnect Performance with Latest PHY Delivering Data Rate of 64Gbps on 3nm Process Using Standard Packaging
- Eliyan Breaks Chiplet Memory Wall With Standard Packaging
Latest News
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