Chiplet Standard Goes 3D
By Gary Hilson, EETimes (September 9, 2024)
The standards governing chiplet technology now have a second iteration.
The Universal Chiplet Interconnect Express (UCIe) Consortium, which was formed in March 2022, recently released its 2.0 specification with updates that address design challenges for testability, manageability and debug (DFx) for the SiP lifecycle across multiple chiplets. A key feature of the update is support for 3D packaging to enable chiplets to dramatically increase bandwidth density and power efficiency.
In a briefing with EE Times, consortium chair Debendra Das Sharma said that the UCIe 2.0 specification is fully backward compatible, while introducing optional manageability features and a UCIe DFx Architecture (UDA) that supports vendor agnostic chiplet interoperability.
The consortium has spread work on the specification across several working groups that focus on different aspects, including electrical, protocol, form factor and compliance, manageability and security, and systems and software. Das Sharma said a recently formed automative working group reflects an interest from that sector to start gathering requirements.
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