NAPMP announces chiplets R&D area
By Pradeep Chakraborty, Pradeep’s TechPoints (November 5, 2024)
At the recently-held CHIPS National Advanced Packaging Manufacturing Program (NAPMP) Proposer’s Day, an R&D area was chiplets.
Bapiraju Vinnakota, NAPMP Program Manager, stated that the key date for submitting concept papers for chiplets was Dec. 20, 2024. Invitation for full application submission will be on a later date.
Today, the industry is moving toward chiplets. Chiplets are a small, functionally targeted semiconductor chip that, when assembled at tight pitch and placement, results in a highly functional subsystem. A single product integrates and assembles multiple chiplets connected to one another through die-to-die interfaces.
The motivation behind chiplets is to build big (reticle busters), build fast (modularity, reuse), build better (optimize function to process node). A chiplets / systems design inflection point is enabled by advanced packaging. Tomorrow’s packages will be more like chips.
To read the full article, click here
Related Chiplet
- Automotive AI Accelerator
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
Related News
- Faraday Unveils 2.5D/3D Advanced Package Service for Chiplets
- A methodology for turning an SoC into chiplets
- Are Chiplets Enough to Save Moore's Law?
- How the Worlds of Chiplets and Packaging Intertwine
Latest News
- NHanced Semiconductors President Robert Patti to Detail “Foundry 2.0” at SEMIEXPO Heartland
- HyperLight Launches TFLN Chiplet™ Platform with Scalable 6-Inch Production and 8-Inch Expansion for Next-Gen AI and Photonics Infrastructure
- Intel’s Embarrassment of Riches: Advanced Packaging
- Challenges In Managing Chiplet Resources
- Global Fab Equipment Investment Expected to Reach $110 Billion in 2025