A methodology for turning an SoC into chiplets
By Nick Flaherty, eeNews Europe (July 25, 2023)
Siemens has developed a workflow methodology for homogeneous disaggregation of SoCs into chiplets using hierarchical device planning.
The key benefit of adopting hierarchy inside of a design is clear – a seemingly large and complex designs can be disaggregated into smaller and easier to manage building blocks based on a collection of attributes such as function and position.
Advancements in IC packaging manufacturing, combined with the exploding costs of designing monolithic ICs on today’s advanced process nodes, have given rise to a growing trend of disaggregating large SoCs into smaller dies and chiplets says Chris Cone at Siemens EDA.
This increased design complexity requires iterative multi-physics analysis during the floorplanning stage and optimization of the design for PPA and cost goals, significantly raising the barrier for project success. Trying to employ traditional package design solutions – where each device is modeled as a single flat entity – is time consuming and unnecessarily risks delaying production.
However many design structures are comprised of repeatable patterns that can be represented as a parameterized object which is a form of hierarchical design capture. In IC packaging there are two key classes of design structures which lend easily to incorporating hierarchy – these are die-to-die signal interfaces and power distribution networks.
To read the full article, click here
Related Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Interconnect Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- Cadence Accelerates SoC, 3D-IC and Chiplet Design for AI Data Centers, Automotive and Connectivity in Collaboration with Samsung Foundry
- BOS Semiconductors Signed Development Contract for ADAS Chiplet SoC with an European OEM
- DreamBig Semiconductor Announces Partnership with Samsung Foundry to Launch Chiplets for World Leading MARS Chiplet Platform on 4nm FinFET Process Technology Featuring 3D HBM Integration to Solve Scale-up and Scale-out Limitations of AI for the Masses
- Honda and Renesas Sign Agreement to Develop High-Performance SoC for Software-Defined Vehicles
Latest News
- YMTC’s Hybrid Bonding Patents: A Key Competitive Factor for Memory Chipmakers
- Baya Systems Celebrates First Year of Hypergrowth After Emerging from Stealth
- Can You Build A Known-Good Multi-Die System?
- BOS Joins VESA and UCIe to Advance Global Standards in Display and Chiplet Technology
- Arteris Accelerates AI-Driven Silicon Innovation with Expanded Multi-Die Solution