Multi-Die Assemblies Complicate Parasitic Extraction
What used to be an afterthought is now a first-order concern for performance and power at the leading edge.
By Ann Mutschler, Semiconductor Engineering | June 12, 2025
The shift from planar designs to multi-die assemblies with complex interconnects is transforming what had become almost an afterthought in the design process into a first-order challenge.
Parasitics include things like inductance, capacitance, and resistance, which have become more problematic at advanced nodes due to increasing logic density, thinner interconnects and insulators, and a spike in the amount of data that needs to be processed, moved, and stored. In order to circumvent the size limitations of a reticle, large chipmakers have shifted away from planar SoCs to multi-die assemblies in custom-designed packages. But in doing so, they have added many more interconnects and complex interactions, making it much harder to identify and mitigate parasitic effects.
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