Multi-Die Design Complicates Data Management
Design data and metadata are ballooning, and no one is quite sure how long to save it or what to delete.
By Adam Kovac, Semi Engineering
February 27th, 2025
The continued unbundling of SoCs into multi-die packages is increasing the complexity of those designs and the amount of design data that needs to be managed, stored, sorted, and analyzed.
Simulations and test runs are generating increasing amounts of information. That raises questions about which data needs to be saved and for how long. During the design process, engineers now must wrestle with the data and metadata of each individual chiplet, the interconnects, the package, and the overall system. This can include multiple substrates, interposers, and non-electrical elements.
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- Synopsys and Samsung Foundry Deepen Collaboration to Accelerate Multi-Die System Design for Advanced Samsung Processes
- Multi-Die Design Pushes Complexity To The Max
- Synopsys and TSMC Pave the Path for Trillion-Transistor AI and Multi-Die Chip Design
- Sarcina Technology advances photonic package design to address key data center challenges
Latest News
- Celestial AI Introduces Photonic Fabric™ Module - World’s First SoC with In-Die Optical Interconnect, Ushering in a New Era of Interconnects
- Amkor Announces New Site for U.S. Semiconductor Advanced Packaging and Test Facility
- Arteris Joins UALink Consortium to Accelerate High-Performance AI Networks Scale Up
- Athos Silicon Chief mSoC™ Architect Francois Piednoel to Present the IEEE World Technology Summit 2025 in Berlin
- Marvell Unveils Industry’s First 64 Gbps/wire Bi-Directional Die-to-Die Interface IP in 2nm to Power Next Generation XPUs