What are the challenges when testing chiplets?
By Jeff Shepard, Microcontroller Tips (March 4, 2024)
Chiplet testing begins with performance simulations during the design process. Compared with monolithic devices, heterogeneous chiplets require more complex testing, including known good die (KGD) testing, final test, and system level test. Success also depends on the implementation of design for test (DfT) based on several IEEE standards.
Chiplet designers need high-speed tools that can quickly and precisely simulate the die-to-die (D2D) interconnects, which are one of the keys to chiplet performance. For an increasing number of chiplets, simulation, and verification that the design meets the specifications of the Universal Chiplet Interconnect Express (UCIe) standard is another key consideration.
Related Chiplet
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
- UCIe based 12-bit 12-Gsps Transceiver
- 400G Transmitter Chiplet for 400G, 800G and 1.6T Pluggable Transceivers
- FPGA Chiplets with 40K -600K LUTS
Related News
- Faraday Unveils 2.5D/3D Advanced Package Service for Chiplets
- A methodology for turning an SoC into chiplets
- Are Chiplets Enough to Save Moore's Law?
- How the Worlds of Chiplets and Packaging Intertwine
Latest News
- EdgeCortix Receives 4 Billion Yen Subsidy from Japan’s NEDO to Advance Energy-Efficient AI Chiplets for Post-5G Communication Systems
- NAPMP announces chiplets R&D area
- Tenstorrent Expands Deployment of Arteris’ Network-on-Chip IP to Next-Generation of Chiplet-Based AI Solutions
- Arm's Data Center Advances: Chiplets, Efficiency & AI Integration
- Chiplets Make Progress Using Interconnects As Glue