Chiplets and the early adopter’s dilemma
A novel PHY may be the answer to the packaging question
By Designing Electronics North America
Early adopters in the chiplet arena face a dilemma. In pursuit of the highest possible performance and density, the most widely discussed chiplet designs depend upon silicon interposers (or their close relatives, embedded silicon bridges) as a substrate for mounting and interconnecting the multiple dice.
Fabricating the inter-die connections on a silicon substrate allows much tighter bump spacing and line spacing, meaning more possible connections per millimeter of die edge, and hence greater inter-die bandwidth per millimeter of die edge. Also, for a given interconnect electronics, silicon offers a higher data rate than conventional organic substrates. For datacenter CPUs and GPUs, where density and performance are non-negotiable and price is secondary, the common belief has been, as one vendor recently said, “without interposers there can be no chiplets.”
To read the full article, click here
Related Chiplet
- Automotive AI Accelerator
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
Related News
- Faraday Unveils 2.5D/3D Advanced Package Service for Chiplets
- A methodology for turning an SoC into chiplets
- Are Chiplets Enough to Save Moore's Law?
- How the Worlds of Chiplets and Packaging Intertwine
Latest News
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
- NHIZ promotes chiplet industry's development and cooperation
- Cadence and TSMC Advance AI and 3D-IC Chip Design with Certified Design Solutions for TSMC’s A16 and N2P Process Technologies
- Breaking the Memory Wall: How d-Matrix Is Redefining AI Inference with Chiplets
- Alphawave Semi Delivers Foundational AI Platform IP for Scale-Up and Scale-Out Networks