Why Electrical Design Matters in Chiplet Architectures – Part Two: UCIe Latency and Security

By Mayank Bhatnagar (Cadence), Manuel Mota (Synopsys) and Dana Neustadter (Synopsys)

September 30, 2025

In part one of this blog, we examined how UCIe™ addresses the fundamentals of electrical design in chiplets: signal integrity, high-speed data transfer, and power delivery. These are the foundations for effective communication, sustained performance, and the efficiency gains that make disaggregation valuable.

In chiplet-based architectures, electrical design is also central to system performance and reliability. Splitting a system into smaller dies offers flexibility, scalability, and cost savings, but only if the electrical connections are carefully managed. Poor signal flow can create bottlenecks, disrupt timing, or expose vulnerabilities that undermine those benefits. Two areas stand out as especially critical: latency and synchronization, which dictate how efficiently chiplets exchange data, and security, since each die-to-die interface introduces new risks around trust, authentication, and data protection, especially when components come from multiple vendors.

This second installment of our blog explores these challenges and the emerging solutions, with a focus on how UCIe provides the framework for scalable, high-performance, and secure multi-die integration.

Latency Challenges - Crossing the Die-to-Die Traffic Jam

One of the biggest hurdles in chiplet design is latency, the delay that occurs when data moves between dies. In a monolithic chip, all communication stays on a single piece of silicon, but in a chiplet-based design, some signals must cross a die-to-die boundary. This depends on how the design is partitioned between silicon dies. Each crossing adds delay, and as more chiplets are added, these delays may accumulate and create performance bottlenecks.

The example of a memory access makes the problem clear. If a processor requests data and the response is even slightly late, the processor must pause, wasting cycles. Multiply this across many interactions, and system performance suffers. The challenge grows when chiplets operate under different conditions, some gated by power, others running at different speeds, or influenced by heat. These variations make it difficult to keep the system synchronized and efficient.

A careful partitioning of the design between dies is key to minimizing crossings of critical signals and to avoiding the accumulation of delays along a critical data flow path. The impact of added latencies can be minimized by careful partitioning but not eliminated, and that is where hardware and protocol solutions step in, which the industry is actively advancing. At the physical level, engineers are creating low-latency, high-throughput interconnects and improving packaging to reduce distance and improve signal integrity. Smarter clock distribution also helps chiplets stay aligned despite variations. At the protocol level, proven standards like PCIe and CXL are layered on top of UCIe, ensuring consistency and coherency. Lightweight alternatives mapping common NoC protocols (e.g., AXI, CXS.B, CHI-C2C) to UCIe streaming enable even lower latency. This combined approach manages latency through both faster links and smarter coordination.

Synchronization as a Latency Issue

Latency isn’t just about how fast data travels; it is also about synchronization, whether chiplets stay in step with each other. If one chiplet is ready to transmit but its partner is still waiting for power or a security check, communication stalls. UCIe prevents these mismatches by setting strict timing rules: paired chiplets must come online within a defined millisecond-scale window, or the link times out. This keeps chiplets from waiting indefinitely and reduces unpredictable delays. The UCIe standard does this in a couple of ways:

Predictable Startup Behavior

• To make startup more reliable, UCIe enforces a structured handshake process or security authorization. In large packages, some chiplets may depend on others for power sequencing or security approval. Without clear rules, these dependencies could leave the system stuck. UCIe solves this by requiring chiplets to establish links within a fixed timeframe, ensuring that communication begins predictably and systems scale without startup bottlenecks.

A Layered Approach to Synchronization

• UCIe also manages synchronization through a layered architecture. The lower layers handle timing and link stability, while higher protocols such as PCIe and CXL manage complex tasks like memory sharing and cache coherency. By dividing responsibilities, UCIe reduces and avoids unnecessary complexity and maintains consistent, low-latency data paths across the system. The result is a reliable, low-latency framework that not only minimizes timing mismatches but also supports efficient and scalable chiplet communication.

Together, these features make UCIe a comprehensive framework for chiplet communication. It reduces delays at the physical level, enforces predictable startup behavior, and ensures synchronization through layering. Its flexibility is another advantage: UCIe supports multiple modes such as streaming, PCIe, and CXL, allowing designers to optimize for performance, power, or cost. By breaking latency and synchronization into smaller, well-defined challenges, UCIe provides reliable solutions that scale with system complexity.

Security Challenges - Building Trust Across Chiplets

As chiplet-based designs become more common, security has emerged as a major concern. In a monolithic chip, all the logic is tightly integrated on one piece of silicon, making it difficult to isolate or intercept data paths. With chiplets, however, signals must travel across die-to-die links that are easier to identify and probe. Each of these interfaces is part of an expanded attack surface, whether for intercepting sensitive information or tampering with communication to inject malicious data or interfere with availability.

The risk grows even larger in an open chiplet marketplace, where designers may combine components from multiple vendors. Without trust in the supply chain, a counterfeit or malicious chiplet could be introduced, embedding hidden logic designed to snoop on, or spoof (alter) data flows or hijack communications between chiplets. Additionally, chiplets are also vulnerable to side-channel attacks, such as probing voltage levels on interconnect lines to extract sensitive data. A weakness discovered in one multi-die system due to a poorly designed chiplet might be common to all products that also use that same chiplet.

The semiconductor industry is responding to these threats with hardware and protocol-level defenses. At the physical level, techniques like scrambling and noise injection obscure raw signals, making intercepted data unreadable. Secure enclaves with hardware-based roots of trust are being added to chiplets to verify their authenticity and safeguard sensitive operations. At the protocol level, end-to-end encryption and authentication between chiplets ensure that even if data is captured, leaked, or modified, it cannot be interpreted or altered without detection. These measures protect both the integrity and confidentiality of information as it travels across dies, and help protect against the case of one weak chiplet compromising the whole package.

Another important strategy is isolation and sandboxing, which contain chiplets from less-trusted sources so they cannot compromise the entire package. By treating each chiplet as a potentially untrusted element and enforcing strict boundaries, designers limit the damage if a malicious or compromised component slips through the supply chain. Together, these techniques create multiple layers of defense, stretching from the physical wires of the interconnect up through system-level management, making chiplet architectures far more resilient against attacks.

Strengthening Chiplet Security Through UCIe

The UCIe standard incorporates many of these ideas directly into its architecture. At the physical layer, UCIe supports techniques like scrambling, which make side-channel probing far more difficult. At the protocol layer, it defines security hooks for authentication, integrity checks, and encrypted communication, ensuring that chiplets boot up in a secure state and can exchange data securely across die boundaries. These provisions allow sensitive information, such as authorization signals, personal or enterprise private data, or financial transactions, to move between chiplets without being exposed to tampering or compromise.

UCIe also benefits from its layered design, which allows security to be addressed at multiple points in the stack. For example, while the physical and link layers protect signal integrity, higher layers such as CXL can manage secure data sharing and coherency. Features in the UCIe 3.0 specification and previous specifications go even further, introducing support for AES-based encryption, secure encapsulation of data packets, and even emergency shutdown mechanisms if a chiplet behaves suspiciously. By building these capabilities into the standard itself, UCIe provides designers with a common framework to harden their systems against both physical and digital attacks.

Conclusion

Chiplet architectures promise greater scalability and performance, but face two major hurdles: latency and security. Crossing die-to-die boundaries adds delays that must be carefully synchronized, while disaggregation exposes new attack surfaces and supply chain risks. Industry solutions, such as faster interconnects, encryption, and secure enclaves with a hardware root of trust, help, but true progress depends on a unified framework. UCIe delivers that foundation. With predictable startup rules, layered synchronization, and built-in security hooks, it ensures efficient and trusted communication across dies. As an open standard, UCIe gives companies a reliable foundation to address electrical design challenges, fostering interoperability and enabling them to innovate with chiplets that scale into the next era of high-performance, secure computing.

Download the latest UCIe specification to explore the technical details behind secure, high-performance chiplet integration.

To help shape the future of chiplet ecosystems and security, become a UCIe member today.