Why Electrical Design Matters in Chiplet Architectures – Part One: Signal Integrity and Power Delivery

By Mayank Bhatnagar (Cadence), Soheil Modirzadeh (Synopsys) and Sajani Patel (Synopsys)

September 4, 2025

As the semiconductor industry accelerates toward chiplet-based architectures to meet growing performance demands, electrical design considerations are becoming more important. Disaggregating monolithic chips into modular chiplets offers flexibility, better yield, and the ability to mix and match best-in-class IP blocks. But these advantages come with a new class of electrical challenges that can impact functionality, performance, and power efficiency if not addressed early and holistically.

In this first installment of our two-part series on electrical design in chiplet architectures, we focus on three foundational pillars: signal integrity, high-speed data transfer, and power delivery. These are the bedrock issues that determine whether chiplets can communicate effectively, maintain performance under load, and deliver on the power efficiency and latency gains that drove their adoption in the first place. Engineers must design interconnects that minimize signal loss, manage tight power budgets across multiple dies, and ensure bandwidth and data accuracy.

Signal Integrity and High-Speed Data Transfer Challenges

In monolithic systems, signals move across short, predictable paths on a single die, with well-understood electrical characteristics. But chiplet-based architectures introduce new challenges. Signals now travel across separate dies, passing through substrates, interposers, or using 2.5D solutions like Embedded Multi-Die Interconnect Bridge (EMIB), Chip on Wafer on Substrate (CoWoS), or Fan-Out Chip on Substrate (FOCoS). These longer, more complex routes can cause impedance mismatches, crosstalk, and signal degradation, making it harder to maintain high-speed, high-quality data transfer.

A major concern is that chiplet designers often lack full visibility into the final system. A chiplet might be designed without knowing what transmitter or receiver will be on the other end, or what kind of package will be used. Unknowns, such as channel characteristics and package type make it difficult to accurately model the full signal path. If the simulations don’t match real-world conditions, problems like unexpected bit errors or failed links may only show up after the chiplets are fully assembled, when fixes are costly or impossible.

Despite these new challenges, some principles of signal integrity apply across both monolithic and chiplet-based systems. Simulation tools like SPICE, IBIS-AMI, and electromagnetic solvers remain essential for validating performance. Dielectric and conductor losses must still be accounted for, especially as signaling frequencies climb. In chiplet systems, however, timing closure becomes harder to achieve due to variations between processes or dies, for example, connecting a 3nm chiplet to a 28nm one. These mismatches increase the number of cases that designers must check, which can lead to overdesign and impact performance, power, or area.

This is where UCIe™ (Universal Chiplet Interconnect Express™) provides real value. UCIe does not mandate specific packaging technologies but offers a clear, shared reference channel and signal integrity targets for voltage levels, crosstalk, and bit error rates. This specification allows chiplet developers and system integrators to align on common expectations, even when building across vendors or nodes. With UCIe, the industry gets a scalable foundation for achieving reliable, high-speed chiplet-to-chiplet communication, without needing to reinvent the modeling and testing process for every design.

Power Delivery and Efficiency Challenges

Power delivery in chiplet designs is more complex than in traditional chips. In a monolithic chip, all power needs are planned and controlled as a single unit. But in chiplet systems, different chiplets may have different power demands, and those demands can change depending on how they interact. A chiplet might behave one way on its own but draw more or less power depending on what it’s connected to. This makes it hard to predict how much power each chiplet will need at any given time.

Another issue is noise. One chiplet may create power supply noise that affects its neighbors. For example, a high-power chiplet might cause voltage drops or spikes that lead to errors in other chiplets nearby. In some cases, chiplets must go through repeated training steps to establish a connection, and this process, especially when something goes wrong, can unexpectedly increase power use. That extra power not only reduces efficiency but can lead to signal problems and a higher error rate.

To manage these risks, designers use techniques like power gating, advanced voltage regulation, and fine-grain power domain control. These tools let each chiplet control when and how much power it uses, depending on the task it’s performing. They also help reduce waste and keep the system cooler. These techniques have been used in monolithic chips, but now they’re being adapted to work in chiplet environments where power needs are more varied and less predictable.

Thermal management is another growing challenge, especially as chiplets are stacked on top of each other in 3D designs. Heat must be moved away efficiently to avoid overheating. One effective solution is co-design, where silicon, packaging, and power delivery are planned together. This works best when one company designs the whole system. But as the industry moves toward open chiplet marketplaces, where chiplets come from different vendors, power delivery and thermal design become harder to coordinate. Standards like UCIe help by setting limits on power noise and defining how much variation is acceptable, giving designers a reliable starting point.

Standardizing Chiplet Interfaces for a Solid Ecosystem

As chiplet-based architectures continue to evolve, managing electrical design at the die-to-die level is foundational. From signal integrity to power delivery, the shift from monolithic systems to multi-die configurations introduces new challenges that demand tighter collaboration, better modeling, and clear industry standards. UCIe is playing a critical role in creating that shared framework, giving designers a consistent target to aim for, even in a diverse, multi-vendor ecosystem. By defining clear electrical and protocol expectations, signal integrity is easier to model and manage across chiplet-to-chiplet links.

But electrical design doesn’t stop at performance and power; it’s also a cornerstone of system-level trust. In part two of this blog, we’ll examine how inter-die interfaces introduce new security risks, making signal integrity a vital part of the security equation. As performance, reliability, and security converge, electrical design must become a first line of defense from the start. Stay tuned!