What’s happening with current and future chiplet security?

By Pradeep Chakraborty

March 20, 2024

Electronic System Design Alliance (ESDA), part of SEMI, USA, organized a conference today on chiplet security — current and future.

Many semiconductor-based systems are moving toward 2.5D and 3D designs consisting of different pre-manufactured chips (chiplets) that perform specific functions. These are often provided by multiple vendors, and are typically interconnected using an interposer.

However, unlike monolithic multi-function chips, chiplets can be developed anywhere and at any process node. As such, chiplets from untrusted vendors can be unreliable or malicious. Third parties can reverse engineer, overproduce, or steal the IP of chiplets. Consequently, they raise new security challenges for an industry still figuring out ways to effectively mitigate hardware security threats to monolithic chips.

There are potential threats at different stages of bringing chiplets to life, including design, assembly, and testing. The panelists assessed current safeguards to mitigate these risks and discussed open challenges for the industry and academia.

Bob Smith, Executive Director, ESD Alliance, the SEMI Strategic Association Partner, welcomed everyone, and introduced the panelists.

The panelists were: Serge Leef, Head of Secure Microelectronics, Microsoft, Dr. Swarup Bhunia, Semmoto-endowed Prof. and Director, Warren B. Nelms Institute, Salman Nasir, Senior Technical Program Manager, Battelle, John Hallman, Digital Verification Technology Solutions Manager, Siemens EDA, Ming Zhang, VP of R&D Acceleration, PDF Solutions, and Steve Carlson, Director/Solutions Architect, Aerospace and Defense Solutions, Cadence Design Systems. Raj Gautam Dutta, CEO, Silicon Assurance, was the moderator.

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